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M

Mr. Dubey • 65.25K Points
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Q. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.

(A) toggle
(B) set
(C) reset
(D) not change
  • Correct Answer - Option(A)
  • Views: 227
  • Filed under category Digital Electronics and Logic Design
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