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Q. The effectiveness of the cache memory is based on the property of ______

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Q. In which cycle the memory is read and the contents of memory at the address containedin the PC register are loaded into in to IR.

Q. The addressing mode/s, which uses the PC instead of a general purpose register is _____

Q. The signals are grouped such that mutually exclusive signals are put together.

Q. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when occurs.

Q. The access time is composed of

Q. The reason for the implementation of the cache memory is _______

Q. In full adders the sum circuit is implemented using _______

Q. ______ is used to detect and correct the errors that may occur during data transfers.