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Dear candidates you will find MCQ questions of Computer Architecture here. Learn these questions and prepare yourself for coming examinations and interviews. You can check the right answer of any question by clicking on any option or by clicking view answer button.

M

Mr. Dubey • 51.17K Points
Coach

Q. 571) The drawback of building a large memory with DRAM is                               

(A) the large cost factor
(B) the inefficient memory organisation
(C) the slow speed of operation
(D) all of the mentioned
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M

Mr. Dubey • 51.17K Points
Coach

Q. 572) To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.

(A) true
(B) false
(C) ---
(D) ---
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M

Mr. Dubey • 51.17K Points
Coach

Q. 573) The fastest data access is provided using                 

(A) caches
(B) dram’s
(C) sram’s
(D) registers
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M

Mr. Dubey • 51.17K Points
Coach

Q. 574) In set-associative technique, the blocks are grouped into               sets.

(A) 4
(B) 8
(C) 12
(D) 6
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M

Mr. Dubey • 51.17K Points
Coach

Q. 575) A control bit called                     has to be provided to each block in set- associative.

(A) idol bit
(B) valid bit
(C) reference bit
(D) all of the mentioned
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M

Mr. Dubey • 51.17K Points
Coach

Q. 576) The bit used to indicate whether the block was recently used or not is

(A) idol bit
(B) control bit
(C) reference bit
(D) dirty bit
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M

Mr. Dubey • 51.17K Points
Coach

Q. 577) Data which is not up-to date is called as                 

(A) spoilt data
(B) stale data
(C) dirty data
(D) none of the mentioned
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M

Mr. Dubey • 51.17K Points
Coach

Q. 578) The main memory is structured into modules each with its own address register called               

(A) abr
(B) tlb
(C) pc
(D) ir
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M

Mr. Dubey • 51.17K Points
Coach

Q. 579) When consecutive memory locations are accessed only one module is accessed at a time.

(A) true
(B) false
(C) ---
(D) ---
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M

Mr. Dubey • 51.17K Points
Coach

Q. 580) In memory interleaving, the lower order bits of the address is used to

(A) get the data
(B) get the address of the module
(C) get the address of the data within the module
(D) none of the mentioned
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