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Dear candidates you will find MCQ questions of Computer Architecture here. Learn these questions and prepare yourself for coming examinations and interviews. You can check the right answer of any question by clicking on any option or by clicking view answer button.

M

Mr. Dubey • 51.17K Points
Coach

Q. 581) The number successful accesses to memory stated as a fraction is called as

(A) hit rate
(B) miss rate
(C) success rate
(D) access rate
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M

Mr. Dubey • 51.17K Points
Coach

Q. 582) The number failed attempts to access memory, stated in the form of a fraction is called as                     

(A) hit rate
(B) miss rate
(C) failure rate
(D) delay rate
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M

Mr. Dubey • 51.17K Points
Coach

Q. 583) In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when            occurs.

(A) delay
(B) miss
(C) hit
(D) delayed hit
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M

Mr. Dubey • 51.17K Points
Coach

Q. 584) In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of

(A) hit
(B) miss
(C) delay
(D) none of the mentioned
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M

Mr. Dubey • 51.17K Points
Coach

Q. 585) If hit rates are well below 0.9, then they’re called as speedy computers.

(A) true
(B) false
(C) ---
(D) ---
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Mr. Dubey • 51.17K Points
Coach

Q. 586) The extra time needed to bring the data into memory in case of a miss is called as                       

(A) delay
(B) propagation time
(C) miss penalty
(D) none of the mentioned
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Mr. Dubey • 51.17K Points
Coach

Q. 587) The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.

(A) true
(B) false
(C) ---
(D) ---
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Mr. Dubey • 51.17K Points
Coach

Q. 588) The CPU is also called as                   

(A) processor hub
(B) isp
(C) controller
(D) all of the mentioned
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M

Mr. Dubey • 51.17K Points
Coach

Q. 589) A common strategy for performance is making various functional units operate parallelly.

(A) true
(B) false
(C) ---
(D) ---
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M

Mr. Dubey • 51.17K Points
Coach

Q. 590) The PC gets incremented

(A) after the instruction decoding
(B) after the ir instruction gets executed
(C) after the fetch cycle
(D) none of the mentioned
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