Computer Architecture MCQs and Notes

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Indresh Gehalot • 10.11K Points
Tutor II

Q 21. In set associative and associative mapping there exists less flexibility.

(A) true
(B) false
(C) ---
(D) ---

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Indresh Gehalot • 10.11K Points
Tutor II

Q 22. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when            occurs.

(A) delay
(B) miss
(C) hit
(D) delayed hit

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Indresh Gehalot • 10.11K Points
Tutor II

Q 23. The directly mapped cache no replacement algorithm is required.

(A) true
(B) false
(C) ---
(D) ---

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Indresh Gehalot • 10.11K Points
Tutor II

Q 24. Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is

(A) horizontal organisation
(B) vertical organisation
(C) diagonal organisation
(D) none of the mentioned

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Indresh Gehalot • 10.11K Points
Tutor II

Q 25. The signals are grouped such that mutually exclusive signals are put together.

(A) true
(B) false
(C) ---
(D) ----

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Indresh Gehalot • 10.11K Points
Tutor II

Q 26. To increase the speed of memory access in pipelining, we make use of _____

(A) Special memory locations
(B) Special purpose registers
(C) Cache
(D) Buffers

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Indresh Gehalot • 10.11K Points
Tutor II

Q 27. Each stage in pipelining should be completed within ____ cycle.

(A) 1
(B) 2
(C) 3
(D) 4

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Indresh Gehalot • 10.11K Points
Tutor II

Q 28. The fetch and execution cycles are interleaved with the help of _____

(A) Modification in processor architecture
(B) Clock
(C) Special unit
(D) Control unit

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Indresh Gehalot • 10.11K Points
Tutor II

Q 29. _____ has been developed specifically for pipelined systems.

(A) Utility software
(B) Speed up utilities
(C) Optimizing compilers
(D) None of the mentioned

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Indresh Gehalot • 10.11K Points
Tutor II

Q 30. ______ is used to detect and correct the errors that may occur during data transfers.

(A) ecc
(B) crc
(C) checksum
(D) none of the mentioned

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