Digital Principles and System Design MCQs | Page - 4

 a full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. thus three inputs and two outputs (sum and carry) are there. in case of half adder circuit, there are only two inputs bits and two outputs (sum and carry).

 there are three product terms. so, three and gates of two inputs are required. as only two input or gates are available, so two or gates are required to get the logical sum of three product terms.

 the nand & nor gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates and, or and not.

 1st output of and gate is = a’b’ 2nd and gate’s output is = ab and,

 sop means sum of products form which represents the sum of product terms having variables in complemented as well as in uncomplemented form. here, the diagram of d contains the or gate followed by the and gates, so it is in sop form.

 the two result obtained is 0 with a carry of 1. this carry is transferred to the next higher column.

 the binary multiplication of any number with 0 will give the result 0 itself. any binary number when multiplied by 0 gives 0 only.

 111 is called the multiplier.

 the intermediate terms are called partial terms. the mid terms obtained in the binary multiplications are the partial ones whereas the answer obtained is called the final product.

 it is referred to as underflow. nan stands for not a number. mantissa is the part after the decimal.