Computer Architecture
I
Q 51. The part of machine level instruction, which tells the central processor what has to be done, is
I
Q 52. In which cycle the memory is read and the contents of memory at the address containedin the PC register are loaded into in to IR.
I
Q 53. The address space is 22 bits the memory is 32 bit word addressable what is the memory size
I
Q 54. The copy-back protocol is used _______
I
Q 55. The correspondence between the main memory blocks and those in the cache is given by ________
I
Q 56. The spatial aspect of the locality of reference means ______
I
Q 57. The effectiveness of the cache memory is based on the property of ______
I
Q 58. The reason for the implementation of the cache memory is _______
I
Q 59. ___ addressing mode is most suitable to change the normal sequence of execution of instructions.
I