Computer Architecture

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Indresh • 9.81K Points
Tutor III

Q 61. The addressing mode which makes use of in-direction pointers is ___

(A) Indirect addressing mode
(B) Index addressing mode
(C) Relative addressing mode
(D) Offset addressing mode
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Indresh • 9.81K Points
Tutor III

Q 62. In the case of, Zero-address instruction method the operands are stored in __

(A) Registers
(B) Accumulators
(C) Push down stack
(D) Cache
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Indresh • 9.81K Points
Tutor III

Q 63. The instruction, Add #45, R1 does _____

(A) Adds the value of 45 to the address of R1 and stores 45 in that address
(B) Adds 45 to the value of R1 and stores it in R1
(C) Finds the memory location 45 and adds that content to that of R1
(D) None of the mentioned
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Indresh • 9.81K Points
Tutor III

Q 64. The method which offers higher speeds of I/O transfers is _________

(A) Interrupts
(B) Memory mapping
(C) Program-controlled I/O
(D) DMA
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Indresh • 9.81K Points
Tutor III

Q 65. To overcome the lag in the operating speeds of the I/O device and the processor we use ______

(A) Buffer spaces
(B) Status flags
(C) Interrupt signals
(D) Exceptions
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Indresh • 9.81K Points
Tutor III

Q 66. The system is notified of a read or write operation by _________

(A) Appending an extra bit of the address
(B) Enabling the read or write bits of the devices
(C) Raising an appropriate interrupt signal
(D) Sending a special signal along the BUS
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Indresh • 9.81K Points
Tutor III

Q 67. The advantage of I/O mapped devices to memory mapped is _______

(A) The former offers faster transfer of data
(B) The devices connected using I/O mapping have a bigger buffer space
(C) The devices have to deal with fewer address lines
(D) No advantage as such
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Indresh • 9.81K Points
Tutor III

Q 68. The usual implementation of the carry circuit involves ______

(A) And & or gates
(B) XOR
(C) NAND
(D) XNOR
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Indresh • 9.81K Points
Tutor III

Q 69. In full adders the sum circuit is implemented using _______

(A) And & or gates
(B) NAND gate
(C) XOR
(D) XNOR
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Indresh • 9.81K Points
Tutor III

Q 70. Which option is true regarding the carry in the ripple adders?

(A) Are generated at the beginning only
(B) Must travel through the configuration
(C) Is generated at the end of each operation
(D) None of the mentioned
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