Digital Electronics MCQs and Notes

R

Ranjeet • 34.60K Points
Instructor I

Q 1. A Schmitt trigger has VT+ = 2.0 V and VT– = 1.2 V. What is the hysteresis voltage of the Schmitt trigger?

(A) 0.4 volt

(B) 0.6 volt

(C) 0.8 volt

(D) 1.2 volts

A

Admin • 36.93K Points
Coach

Q 2. Why would a delay gate be needed for a digital circuit?

(A) a delay gate is never needed.

(B) to provide for setup times

(C) to provide for hold times

(D) to provide for setup times and hold times

R

Ram Sharma • 193.84K Points
Coach

Q 3. The ________ circuit overcomes the problem of switching caused by jitter on the inputs.

(A) astable multivibrator

(B) monostable multivibrator

(C) bistable multivibrator

(D) schmitt trigger

R

Rakesh Kumar • 28.44K Points
Instructor II

Q 4. How many flip-flops are required to produce a divide-by-128 device?

(A) 1

(B) 4

(C) 6

(D) 7

S

Shiva Ram • 30.44K Points
Instructor I

Q 5. How many flip-flops are in the 7475 IC?

(A) 1

(B) 2

(C) 4

(D) 8

R

Ranjeet • 34.60K Points
Instructor I

Q 6. How is a J-K flip-flop made to toggle?

(A) j = 0, k = 0

(B) j = 1, k = 0

(C) j = 0, k = 1

(D) j = 1, k = 1

R

Rakesh Kumar • 28.44K Points
Instructor II

Q 7. Propagation delay time, tPLH, is measured from the ________.

(A) triggering edge of the clock pulse to the low-to-high transition of the output

(B) triggering edge of the clock pulse to the high-to-low transition of the output

(C) preset input to the low-to-high transition of the output

(D) clear input to the high-to-low transition of the output

V

Vinay • 28.75K Points
Instructor II

Q 8. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

(A) the logic level at the d input is transferred to q on ngt of clk.

(B) the q output is always identical to the clk input if the d input is high.

(C) the q output is always identical to the d input when clk = pgt.

(D) the q output is always identical to the d input.

R

Rakesh Kumar • 28.44K Points
Instructor II

Q 9. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

(A) 10.24 khz

(B) 5 khz

(C) 30.24 khz

(D) 15 khz

R

Ranjeet • 34.60K Points
Instructor I

Q 10. Settling time is normally defined as the time it takes a DAC to settle within ________.

(A) 1/8 lsb of its final value when a change occurs in the input code

(B) 1/4 lsb of its final value when a change occurs in the input code

(C) 1/2 lsb of its final value when a change occurs in the input code

(D) 1 lsb of its final value when a change occurs in the input code