Digital Principles and System Design MCQs | Page - 16

 it is completely possible to detect the clock edge (positive or negative) by any other method than if statement. one can use the wait statement to detect either of the edge of the clock pulse.

 sequential circuits are represented as finite state machine and may be modelled as combinational logic.

 sequential circuit includes a set of delays and feedback from output to input and it is known as finite state machine.

 the ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit.

 next state and output are both functions of present state and the independent inputs.

 in clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays.

 the circuit propagation delays contribute to the necessary delay elements. the delay in the feedback path may be non-existence.

 in an or gate, if struck at 1 fault in present in b path then output will always be 1.

 the iterative test generation methods are best suited to logic with few feedback loops as in control logic for example.

 iterative test generation method is time consuming for circuits of any complexity. it is