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Digital Logic Circuits (DLC) MCQs | Page - 13

Dear candidates you will find MCQ questions of Digital Logic Circuits (DLC) here. Learn these questions and prepare yourself for coming examinations and interviews. You can check the right answer of any question by clicking on any option or by clicking view answer button.

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Q. 121) Three decade counter would have                          

(A) 2 bcd counters
(B) 3 bcd counters
(C) 4 bcd counters
(D) 5 bcd counters
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Q. 122) BCD counter is also known as                          

(A) parallel counter
(B) decade counter
(C) synchronous counter
(D) vlsi counter
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Q. 123) The parallel outputs of a counter circuit represent the                            

(A) parallel data word
(B) clock frequency
(C) counter modulus
(D) clock count
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Q. 124) The time from the beginning of a read cycle to the end of tACS/tAA is called as

(A) write enable time
(B) data hold
(C) read cycle time
(D) access time
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Q. 125) Why did PROM introduced?

(A) to increase the storage capacity
(B) to increase the address locations
(C) to provide flexibility
(D) to reduce the size
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Q. 126) A variable on its own or in its complemented form is known as a                      

(A) product term
(B) literal
(C) sum term
(D) word
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Q. 127) Canonical form is a unique way of representing                          

(A) sop
(B) minterm
(C) boolean expressions
(D) pos
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Q. 128) There are Minterms for 3 variables (a, b, c).

(A) 0
(B) 2
(C) 8
(D) 1
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Q. 129) Why is a demultiplexer called a data distributor?

(A) the input will be distributed to one of the outputs
(B) one of the inputs will be selected for the output
(C) the output will be distributed to one of the inputs
(D) single input gives single output
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Q. 130) Most demultiplexers facilitate which type of conversion?

(A) decimal-to-hexadecimal
(B) single input, multiple outputs
(C) ac to dc
(D) odd parity to even parity
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