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Mr. Dubey • 51.17K Points
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Q. 61) With regard to a D latch

(A) the q output follows the d input when en is low
(B) the q output is opposite the d input when en is low
(C) the q output follows the d input when en is high
(D) the q output is high regardless of en’s input state
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Mr. Dubey • 51.17K Points
Coach 

Q. 62) Which of the following is correct for a D latch?

(A) the output toggles if one of the inputs is held high
(B) q output follows the input d when the enable is high
(C) only one of the inputs can be high at a time
(D) the output complement follows the input when enabled
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Mr. Dubey • 51.17K Points
Coach 

Q. 63) Which of the following describes the operation of a positive edge-triggered D flip-flop?

(A) if both inputs are high, the output will toggle
(B) the output will follow the input on the leading edge of the clock
(C) when both inputs are low, an invalid state exists
(D) the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
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Mr. Dubey • 51.17K Points
Coach 

Q. 64) A positive edge-triggered D flip-flop will store a 1 when

(A) the d input is high and the clock transitions from high to low
(B) the d input is high and the clock transitions from low to high
(C) the d input is high and the clock is low
(D) the d input is high and the clock is high
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Mr. Dubey • 51.17K Points
Coach 

Q. 65) Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?

(A) due to its capability to receive data from flip-flop
(B) due to its capability to store data in flip-flop
(C) due to its capability to transfer the data into flip-flop
(D) due to erasing the data from the flip-flop
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Mr. Dubey • 51.17K Points
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Q. 66) The characteristic equation of D-flip-flop implies that

(A) the next state is dependent on previous state
(B) the next state is dependent on present state
(C) the next state is independent of previous state
(D) the next state is independent of present state
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Mr. Dubey • 51.17K Points
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Q. 67) The asynchronous input can be used to set the flip-flop to the

(A) 1 state
(B) 0 state
(C) either 1 or 0 state
(D) forbidden state
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Mr. Dubey • 51.17K Points
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Q. 68) Input clock of RS flip-flop is given to

(A) input
(B) pulser
(C) output
(D) master slave flip-flop
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Mr. Dubey • 51.17K Points
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Q. 69) D flip-flop is a circuit having

(A) 2 nand gates
(B) 3 nand gates
(C) 4 nand gates
(D) 5 nand gates
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Mr. Dubey • 51.17K Points
Coach 

Q. 70) At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

(A) conversion condition
(B) race around condition
(C) lock out state
(D) forbidden state
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